Power MOSFET devices typically include a plurality of individual MOSFETs fabricated in a pattern to form a MOSFET array. Advances in high-resolution lithography permit individual MOSFETs in the array to be densely grouped together on a semiconductor substrate, increasing the total number of individual MOSFETs per unit area. Theoretically, a higher number of individual MOSFETs operating in parallel within a single MOSFET array will decrease the overall on-state resistance in the MOSFET array. In practice, however, there are various technical and geometric limitations on closely packed MOSFETs in a MOSFET array. For instance, the use of MOSFET devices in power conversion systems is limited by the on-state resistance per unit area, the input capacitance per unit area, the gate resistance per unit area, the source-to-drain withstand voltage capacity, the packaging inductance and external interconnects, and the thermal conductivity to remove heat from the semiconductor device.
For a semiconductor device having small geometries, such as a MOSFET device having lithographically defined gate lengths of less than 1 um, the on-state resistance can be the limiting factor due to the noticeable contribution of resistance from the overlying metal interconnect layers carrying electric current to the source and drain regions. The impact of on-state resistance is even more pronounced for power MOSFET devices because the dimensions required to optimize the on-state resistance for the small geometry components are not compatible with the large amount of current carried by some power MOSFET devices.